PLL602-01 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise XO (24MHz to 50MHz)

PLL602-01
Low Phase Noise XO (24MHz to 50MHz)
FEATURES
• Low phase noise XO output for the 24MHz to
50MHz range (-135 dBc at 10kHz offset).
• 12 to 25MHz crystal input.
• Integrated crystal load capacitor: no external
load capacitor required.
• Low jitter (RMS): 3ps period jitter (1 sigma).
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• 3.3V operation.
• Available in 8-Pin TSSOP or SOIC.
DESCRIPTION
The PLL602-01 is a low cost, high performance and
low phase noise XO, providing less than -135dBc at
10kHz offset in the 24MHz to 50MHz operating
range. The very low jitter (3ps RMS period jitter)
makes this chip ideal for applications requiring clean
reference frequency sources. Input crystal can range
from 12 to 25MHz (fundamental resonant mode).
BLOCK DIAGRAM
PIN CONFIGURATION
CLK 1
VDD 2
OE^ 3
XIN 4
8 GND
7 GND
6 N/C
5 XOUT
^: Denotes internal pull-up
OUTPUT RANGE
MULTIPLIER
x2
FREQUENCY
RANGE
24 - 50MHz
OUTPUT
BUFFER
CMOS
Reference
Divider
XIN
XOUT
XTAL
OSC
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1