PLL601-15 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise PLL Clock Multiplier

Preliminary PLL601-15
Low Phase Noise PLL Clock Multiplier
FEATURES
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels.
• Reference 20-30MHz crystal or clock.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 150MHz at 3.3V.
• Low phase noise (-126dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 8-Pin SOIC or TSSOP.
DESCRIPTIONS
The PLL601-15 is a low cost, high performance and
low phase noise clock synthesizer. It implements
PhaseLink’s proprietary analog and digital Phase
Locked Loop techniques for a fixed 5x multiplier.
The chip accepts crystal or clock inputs ranging from
20 to 30MHz, and produces outputs clocks up to
150MHz at 3.3V.
PIN CONFIGURATION
XIN 1
GND 2
GND 3
GND 4
8 XOUT
7 VDD
6 VDD
5 CLK
CRYSTAL RANGE
Multiplier
5x
Xtal range
20-30MHz
BLOCK DIAGRAM
XIN
XOUT
Phase
Locked
Loop
XTAL
OSC
CLK
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Rev 01/08/02 Page 1