PLL601-12 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Dual Output PLL Clock with Selectable Odd Multiplier

PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
FEATURES
• Selectable multipliers (x2.5, x2.75, x3, x4.25, x5,
x5.5, x5.75, x6, x6.25, x10, x11, x11.5, x12,
x12.5).
• Crystal input range, 13MHz to 31MHz (see Se-
lection Table for detailed acceptable input
ranges).
• Maximum output frequency: 312.5MHz
• 2 CMOS outputs.
• Selectable output drive (Standard or High-Drive).
• Selectable REF_CLK output.
• 3.3V operation.
• Available in 14-Pin SOIC.
DESCRIPTION
PIN CONFIGURATION
(Top View)
VDD 1
XIN 2
XOUT 3
S3^ 4
S2^ 5
DRIVE_SEL^ 6
GND 7
14 S0^
13 S1^
12 REF_SEL^
11
CLK2/
REF_CLK
10 VDD
9 CLK1
8 GND
^: Internal pull-up.
The PLL601-12 is a highly flexible XO with select-
able multipliers and two CMOS outputs (one of which
can be selected to be REF_CLK). Thanks to Phase-
Link’s advanced Phase Locked Loop technology, it
allows a wide choice of selectable multipliers that
permits the user to achieve useful frequencies from
standard low cost crystals. It accepts fundamental
parallel resonant mode crystals from 13 to 31MHz,
and is ideal to generate 156.25MHz from a standard
25MHz crystal.
BLOCK DIAGRAM
[S3,S0]
XOUT
XIN
Oscillator
Amplifier
PLL
(Phase
Locked
Loop)
REF_SEL
CLK2/REF_CLK
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1