PLL601-03 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise PLL Clock Multiplier

Preliminary PLL601-03
Low Phase Noise PLL Clock Multiplier
FEATURES
• Full swing CMOS outputs with 25 mA drive
capability at TTL levels.
• Reference 10-30MHz crystal or clock.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 198MHz at 3.3V.
• Low phase noise (-126dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 16-Pin SOIC or TSSOP.
PIN CONFIGURATION
CLK 1
REFEN 2
VDD 3
VDD 4
VDD 5
XOUT 6
S1 7
XIN 8
16 GND
15 GND
14 GND
13 REFOUT
12 OE
11 S0
10 S3
9 S2
DESCRIPTIONS
The PLL601-03 is a low cost, high performance and
low phase noise clock synthesizer. It implements
PhaseLink’s proprietary analog and digital Phase
Locked Loop techniques to allow the user to select
the desired multiplier value. The chip accepts crystal
or clock inputs ranging from 10 to 30MHz, depening
on selected multiplier, and produces outputs clocks
up to 198MHz at 3.3V.
MULTIPLIER SELECT TABLE
S3 S2 S1 S0
0000
0001
0101
1001
1101
Multiplier
Xtal range
Reserved
11x
10–18MHz
5x
20-30MHz
Frequency Pass through
6x
11-22MHz
BLOCK DIAGRAM
S3
S2
S1
S0
XIN
XOUT
ROM Based
Multipliers
Phase
Locked
Loop
XTAL
OSC
OE
CLK
REFOUT
REFEN
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 06/15/01 Page 1