PLL601-02 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise PLL Clock Multiplier

PLL601-02
Low Phase Noise PLL Clock Multiplier
FEATURES
• Low phase noise XO
• Input from crystal or clock at 10-27MHz.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 160MHz.
• Low phase noise (-125dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 16-Pin SOIC or TSSOP.
PIN CONFIGURATION
CLK 1
REFEN 2
VDD 3
VDD 4
VDD 5
XOUT 6
S1^ 7
XIN 8
16 GND
15 GND
14 GND
13 REFOUT
12 OE^
11 S0^
10 S2^
9 GND
DESCRIPTION
The PLL601-02 is a low cost, high performance and
low phase noise clock synthesizer with 4x or 8x mul-
tiplier. Using PhaseLink’s proprietary analog and
digital Phase Locked Loop techniques, this IC can
produce up to a 160MHz out put. Ideal for
155.52MHz applications.
BLOCK DIAGRAM
MULTIPLIER SELECT TABLE
S2 S1 S0
000
001
010
011
100
101
110
111
CLK
Test
Reserved
4x Input (Low Frequency VCO*)
8x Input (Low Frequency VCO*)
Reserved
XO Frequency Pass through
4x Input (High Frequency VCO*)
8x Input (High Frequency VCO*)
*: Low Frequency VCO is advised for best performance at 155.52MHz
S2
ROM Based
S1
Multipliers
S0
VCO
Divider
Reference
Divider
XIN
XOUT
XTAL
OSC
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
REFEN
CLK
REFOUT
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1