PLL601-01 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise PLL Clock Multiplier

PLL601-01
Low Phase Noise PLL Clock Multiplier
FEATURES
• Low phase noise XO
• Input from crystal or clock at 10-27MHz.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output clocks up to 160MHz.
• Low phase noise (-125dBc/Hz @ 1kHz).
• Output Enable function.
• Low jitter (RMS): 7.2ps (period), 11.2ps (accum.)
• Advanced low power sub-micron CMOS process.
• 3.3V operation.
• Available in 16-Pin SOIC or TSSOP.
PIN CONFIGURATION
CLK 1
REFEN 2
VDD 3
VDD 4
VDD 5
XOUT 6
S1^ 7
XIN 8
16 GND
15 GND
14 GND
13 REFOUT
12 OE^
11 S0^
10 S3^
9 S2^
DESCRIPTION
The PLL601-01 is a low cost, high performance and
low phase noise clock synthesizer. Using Phase-
Link’s proprietary analog and digital Phase Locked
Loop techniques, this IC can produce up to a
160MHz output.
Note: ^ denotes internal pull up.
BLOCK DIAGRAM
S3
S2
ROM Based
S1
Multipliers
S0
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
XIN
XOUT
XTAL
OSC
Loop
Filter
VCO
OE
REFEN
CLK
REFOUT
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/03/04 Page 1