PLL600-27T-37T Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Power 3 Outputs XO 10MHz to 52MHz

Preliminary PLL600-27T/-37T
Low Power 3 Outputs XO 10MHz to 52MHz
FEATURES
• 3 CMOS outputs with OE tri-state control
• Low current consumption:
PLL600-27T: <4.5mA @ 27MHz with standard
CMOS buffer (3.3V)
PLL600-37T: <3.0mA @ 27MHz with CMOS
compatible Clipped buffer, offering
the lowest current consumption
(3.3V)
• 10 to 52MHz fundamental crystal input.
• Low phase noise (-130 dBc @ 10kHz offset).
• Low jitter (RMS): 2.5ps period jitter.
• 12mA drive capability at TTL output.
• 1.62V to 3.63V DC operation.
• Available in 8 pin SOIC.
PIN ASSIGNMENT
XIN/FIN 1
OE^ 2
CLK1 3
GND 4
8 XOUT
7 CLK0
6 VDD
5 CLK2
^: Denotes internal Pull-up
DESCRIPTION
The PLL600-27T/-37T form a low cost family of XO
IC’s, designed to replace multiple XO solutions sav-
ing the cost and board space of clock distribution
buffers. In addition, they provide among the lowest
current on the market for the 10MHz to 52MHz
range. They accept input crystals from 10 to 52MHz
(fundamental resonant mode) and provide low phase
noise (<-130dBc at 10kHz offset at 30MHz), and very
low jitter (2.5 ps RMS period jitter) outputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
CLK0
CLK1
CLK2
OE
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 08/12/04 Page 1