PLL600-27M Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Dual XO with 4 CMOS Outputs 10MHz to 52MHz

Preliminary PLL600-27M
Dual XO with 4 CMOS Outputs 10MHz to 52MHz
FEATURES
• Generates 4 CMOS outputs from 2 crystal inputs
• XIN1- Accepts a 10 to 52MHz crystal input
and generates 1 CMOS output at the same
frequency.
• XIN2- Accepts a 10 to 52MHz crystal input
and generates 3 CMOS outputs at the same
frequency.
• Low phase noise (-130 dBc @ 10kHz offset).
• Low jitter (RMS): 2.5ps period jitter.
• 12mA drive capability at TTL output.
• 1.62V to 3.63V DC operation.
• Available in 14 pin 150mil SOIC.
DESCRIPTION
The PLL600-27M is part of PhaseLink ’s low cost
family of XO IC’s, designed to replace multiple XO
solutions saving the cost and board space of clock
distribution buffers. In addition, this product family
provides among the lowest current on the market for
the 10MHz to 52MHz range. They accept input
crystals from 10MHz to 52MHz (fundamental
resonant mode) and provide low phase noise (<-
130dBc at 10kHz offset at 30MHz), and very low
jitter (2.5 ps RMS period jitter) outputs.
PIN ASSIGNMENT
XIN1 1
GND 2
GND 3
CLK2A 4
VDD 5
CLK2B 6
XOUT2 7
14 XOUT1
13 N/C
12 VDD
11 CLK1
10 GND
9 CLK2C
8 XIN2
BLOCK DIAGRAM
XIN1
XOUT1
XTAL
OSC
XIN2
XOUT2
XTAL
OSC
CLK1
CLK2A
CLK2B
CLK2C
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 08/12/04 Page 1