PLL600-27B Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Ultra Low Current XO 10 MHz to 52 MHz

Preliminary PLL600-27B
Ultra Low Current XO 10 MHz to 52 MHz
FEATURES
• Low phase noise (-145 dBc @ 10kHz offset).
• CMOS output with OE tri-state control.
• Ultra Low current consumption ( <2mA, at
27MHz, 3.3V)
• 10 to 52MHz fundamental or 3^rd OT crystal input.
• 12mA drive capability at TTL output.
• Low jitter (RMS): 2.5ps period jitter.
• 1.8V, 2.5V and 3.3V DC operation.
• Available in 8 pin SOIC
DESCRIPTION
The PLL600-27B form a low cost family of XO IC’s,
designed to consume the lowest current on the mar-
ket for the 10MHz to 52MHz range. It accepts fun-
damental resonant mode crystal input from 10 to
52MHz. Providing less than -145 dBc at 10kHz offset
at 30MHz and with a very low jitter (2.5 ps RMS pe-
riod jitter) makes this chip ideal for applications re-
quiring low current frequency sources.
BLOCK DIAGRAM
XIN/FIN
XTAL
XOUT
OSC
OE
OSCSEL
CLK
PIN ASSIGNMENT (PACKAGE)
XIN/FIN 1
OE^ 2
DNC 3
GND 4
8 XOUT
7 DNC
6 VDD
5 CLK
^ : denotes internal pull-up
8-pin SOIC
OE^
GND
XIN/FIN
1⁶
2⁵
3⁴
SOT-23
CLK
VDD
XOUT
PAD LAYOUT
XIN 1
OE 2
DNC 3
GND ₄
(0,0)
Y
X
32 mil
XOUT
8
(812, 986)
7 DNC
6 ^VDD
5
Die ID:
C 500A-0505-05K
CLK
OE LOGIC SELECTION TABLE
OE^
0
1(default)
OUTPUT
Disabled - osc. off
Enabled
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/03/05 Page 1