PLL521-23 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Phase Noise PECL VCXO (100MHz to 200MHz)

PLL521-23
Low Phase Noise PECL VCXO (100MHz to 200MHz)
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100MHz – 200MHz.
• Complementary PECL outputs.
• Selectable OE Logic (enable high or enable low).
• Integrated variable capacitors.
• High pull linearity: < 5%.
• +/- 120 ppm pull range
• Supports 2.5V or 3.3V-Power Supply.
• Available in 16-pinTSSOP and die form.
• Thickness 10 mil.
DESCRIPTION
PLL521-23 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input. The chip provides a
low phase noise, low jitter PECL differential clock
output.
BLOCK DIAGRAM
VCON ^Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
PLL521-23
DIE CONFIGURATION
57.5 mil
(1460,1435)
GNDOSC 18
VCON ¹⁹
XIN ²⁰
XOUT ²¹
OECTRL ²²
17
16
15
14
13
12
11
10
9
8
Die ID: 560A-EEEE-ER
7
1
2
34
56
VDDANA
VDDBUF
VDDBUF
PECLBAR
PECL
GNDBUF
Y ^(0,0)
X
PACKAGE CONFIGURATION
OUTPUT ENABLE LOGIC SELECTION
OESEL*
(Pad/Pin #14)
OECTRL*
(Pad #22, Pin # 6)
State
0 (Default)
0 (Default)
1
Output enabled
Tri-state
1
0
Tri-state
1 (Default)
Output enabled
* Bond to GND to set to “0”, bond to VDD to set to “1”. No connection results
to “default” setting through internal pull-up/-down.
Pad #22, Pin #6: Logical states defined by PECL VIH and VIL levels.
HIGH IMPEDANCE BUFFER LOGIC
SELECTION
BUFZSEL
(Pad/Pin #15)
0 (Default)
State
Hi Z if Output is Disabled
1
(Q=0) +(Qbar=1) if Output Disabled
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
56.5 x 57.5 mil
GND
80 micron x 80 micron
10 mil
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 05/19/05 Page 1