PLL520-40 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 130MHz (no PLL).
• Low Injection Power for crystal 50uW.
• CMOS outputs (High Drive (30mA) or Standard
Drive (10mA) output).
• Integrated variable capacitors.
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTION
The PLL520-40 is a VCXO IC specifically designed
to pull frequency fundamental crystals from 65MHz
to 130MHz, with CMOS outputs. Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
VCON ^Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
OE
Q
PLL520-40
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
XIN 26
XOUT 27
Die ID:
A1313-13C
N/C 28
N/C 29
OE
30
CTRL^
VCON 31
C502A
1 23 4 5
6
78
(1550,1475)
17 GNDBUF
16 CMOS
15 N/C
14 N/C
13 VDDBUF
12 VDDBUF
11 CMOS
10 N/C
9 N/C
Y ^(0,0)
X
Note: ^ denotes internal pull up
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
DRIVE_SEL AND OE_CTRL TABLE
DRIVE_SEL
(Pad #19)
0
1
Output Drive
High Drive CMOS
Standard CMOS (default)
OE_CTRL
(Pad #30)
0
1
State
Tri-state
Output enabled (default)
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1