PLL520-38-39 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 130MHz (no PLL).
• Low Injection Power for crystal 50uW.
• PECL (PLL520-38) or LVDS output (PLL520-39).
• Integrated variable capacitors.
• Supports 2.5V or 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3 QFN).
DESCRIPTION
The PLL520-38/-39 is a family of VCXO IC’s
specifically designed to pull high frequency
fundamental crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs.. They achieve
very low current into the crystal resulting in better
overall stability. Their internal varicaps allow an on
chip frequency pulling, controlled by the VCON
input. Their very low jitter makes them ideal for the
most demanding timing requirements.
BLOCK DIAGRAM
VCON ^Oscillator
Amplifier
w/
XIN _integrated
varicaps
XOUT
OE
Q
Q
PLL520-38/-39
PIN CONFIGURATION
VDD 1
XIN 2
XOUT 3
N/C 4
N/C 5
OE 6
VCON 7
GND 8
16 N/C
15 N/C
14 GND
13 CLKC
12 VDD
11 CLKT
10 N/C
9 N/C
XIN
XOUT
N/C
OE
12 11 10 9
13
8
14
7
P520-3x
15
6
16
5
1234
GND
CLKC
VDD
CLKT
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-38
PLL520-39
OE
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL520-38
Logical states defined by CMOS levels for PLL520-39
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1