PLL520-30 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

Preliminary PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 130MHz (no PLL).
• Low Injection Power for crystal 50uW.
• Complementary outputs: PECL or LVDS.
• Selectable OE Logic
• Integrated variable capacitors.
• Supports 2.5V or 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTIONS
PLL520-30 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
VCON ^Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
PLL520-30
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
26
(1550,1475)
17
16
15
27
14
28
13
29
12
11
30
10
31
9
1 2345
6
78
Y
(0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
0
1
Selected Output
LVDS
PECL (default)
Pad #25 Pad #30
OESEL OE_CTRL
State
0
0
Tri-state
1
Output enabled (default)
1
0
Output enabled (default)
(default)
1
Tri-state
Pad #9, #25 and #30: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
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Rev 4/20/04 Page 1