PLL520-17 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)

PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
• Low Injection Power for crystal 50uW.
• Available outputs: PECL, LVDS, or CMOS.
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in 16 pin (TSSOP or SOIC)
DESCRIPTION
The PLL520-17/-18/-19 family of VCXO IC’s is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
BLOCK DIAGRAM
PIN CONFIGURATION
VDD 1
XIN 2
XOUT 3
SEL3^ 4
SEL2^ 5
OE 6
VCON 7
GND 8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
^: Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-18
PLL520-17
PLL520-19
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
SEL
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
OE
PLL
(Phase
Q
Locked
Q
Loop)
PLL by-pass
PLL520-17/-18/-19
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1