PLL520-00 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz – 1GHz (LVDS output
only for 8x multiplier).
• Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
• Selectable OE Logic (enable high or enable low).
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in die form.
• Thickness 10 mil.
DESCRIPTION
PLL520-00 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
SEL
VCON ^Oscillator
Amplifier
w/
XIN _integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PLL520-00
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 62 mil
GND
80 micron x 80 micron
10 mil
DIE CONFIGURATION
65 mil
25
24 23 22 21
20
19
18
XIN 26
XOUT 27
Die ID:
A1919-19A
SEL3^ 28
SEL2^ 29
OE
30
CTRL
VCON 31
C502A
1 23 4 5
6
78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y ^(0,0)
X
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
OE_SELECT
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
State
Tri-state
Output enabled
Output enabled
Tri-state
Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to
“default” setting through internal pull-up.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “1”
Logical states defined by CMOS levels if OE_SELECT is “0
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/20/04 Page 1