PLL502-67 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – 4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO

Preliminary PLL502-67
4 Outputs 12.5MHz – 200MHz Low Phase Noise Multiplier VCXO
FEATURES
• Selectable 12.5MHz to 200MHz range.
• Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 17.664MHz, -132dBc/Hz
for 35.328MHz, -125dBc/Hz for 155.52MHz).
• 4 CMOS outputs (in phase).
• 12 to 25MHz crystal input.
• No external load capacitor or varicap required.
• Wide pull range (+/-190 ppm)
• Selectable 1/2 to 8x frequency multiplier.
• 3.3V operation.
• Available in 14-SOP.
PIN CONFIGURATION
(Top View)
VDD 1
XIN 2
XOUT 3
SEL2^ 4
SEL1^ 5
VCON 6
GND 7
14 SEL0^
13 CLK4
12 CLK3
11 VDD
10 CLK2
9 CLK1
8 GND
DESCRIPTIONS
The PLL502-67 is high performance and low phase
noise VCXO IC chip. It provides phase noise per-
formance as low as –140dBc at 1kHz offset (at
17.664MHz) and –125dBc at 1kHz offset at
155.52MHz by multiplying the input crystal frequency
up to 8x. The wide pull range (+/- 190 ppm) and very
low jitter makes this chip ideal for a wide range of
applications, from xDSL to SONET/SDH and FEC.
The chip accepts a low cost fundamental parallel
resonant mode crystal from 12 to 25MHz.
^: Internal pull-up
BLOCK DIAGRAM
SEL
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
PLL by-pass
CLK4
CLK3
CLK2
CLK1
PLL502-67
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 02/20/03 Page 1