PLL502-52 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)

PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
FEATURES
• Integrated voltage-controlled crystal oscillator
circuitry (VCXO) (pull range 380ppm minimum).
• VCXO tuning range: 0V - V_DDV.
• Uses inexpensive fundamental-mode parallel
resonant crystals (from 20 to 40MHz).
• Integrated divider by 2: output range of 10MHz
to 20MHz.
• 2.5V or 3.3V supply voltage.
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• Available in 8-Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-52 is a monolithic low jitter, high per-
formance CMOS VCXO IC Die. It allows the control
of the output frequency with an input voltage
(VCON), using a low cost crystal.
This makes the PLL502-52 ideal for a wide range of
applications requiring a VCXO output in the 10MHz
to 20MHz range, using a fundamental crystal ranging
from 20 to 40 MHz.
BLOCK DIAGRAM
PIN CONFIGURATION
XOUT 1
N/C 2
VCON 3
GND 4
8 XIN
7 OE^
6 VDD
5 CLK
Note: ^ denotes internal pull up
OUTPUT RANGE
DIVIDER
÷2
FREQUENCY
RANGE
10 - 20MHz
OUTPUT
BUFFER
CMOS
X IN
XOUT
XTAL
OSC
V A R IC A P
OE
VCON
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 9/17/04 Page 1