PLL502-39U Datasheet, PDF (1/6 Pages) PhaseLink Corporation – 750kHz - 800MHz Low Phase Noise Multiplier VCXO

PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
• Selectable 750kHz to 800MHz range.
• Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
• 12 to 25MHz crystal input.
• No external load capacitor or varicap required.
• Inverted LVDS signal Output Enable selector.
• Wide pull range (+/-200 ppm)
• Selectable 1/16 to 32x frequency multiplier.
• 3.3V operation.
• Available in 16-Pin (TSSOP or 3x3mm QFN).
DESCRIPTION
PIN CONFIGURATION
(Top View)
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14
7
PLL502-39U
15
6
16
5
123 4
GND
CLKC
VDD
CLKT
The PLL502-39U (LVDS) is a high performance and
low phase noise VCXO clock IC. It provides phase
noise performance as low as –125dBc at 10kHz off-
set (at 155MHz), by multiplying the input crystal fre-
quency up to 32x. The wide pull range (+/- 200 ppm)
and very low jitter makes this ideal for a wide range
of applications, including SONET/SDH and FEC.
PLL502-39 accepts fundamental parallel resonant
mode crystals input from 12 to 25MHz.
BLOCK DIAGRAM
Note: ^ designates Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-39U
OE
1
0 (Default)
State
Tri-state
Output enabled
SEL
VCON ^Oscillator
Amplifier
w/
XIN
integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
CLKT
PLL502-39U
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/29/05 Page 1