PLL502-26 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – High Pull-Range VCXO (27MHz) with integrated Audio PLL

PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
FEATURES
• Low phase noise 27MHz VCXO (-135 dBc at
10kHz offset).
• Integrated variable capacitors.
• Wide pull range (+/- 250 ppm).
• Low jitter (RMS): 10ps period.
• Integrated audio Phase Locked Loop.
• Audio clock output (ideal for 8.192MHz,
11.2896MHz, 12.288MHz).
• 27MHz crystal input.
• Audio Reference clock input.
• 3.3V operation.
• Available in 16-Pin SOIC.
PIN CONFIGURATION
N/C* 1
VDD_PLL 2
VDD_VCXO 3
XIN
4
XOUT 5
VCON
6
GND_VCXO
7
GND_PLL
8
1 _N/C*
6
1
GND_27MHz
5
1
OUT_27MHz
4
1
VDD_27MHz
3
1
2
VDD_Audio
1
1
OUT_Audio
1
0
GND_Audio
9 REF_Audio
DESCRIPTION
The PLL502-26 is a low cost, high pull-range and
low phase noise VCXO, providing less than -135dBc
at 10kHz offset at 27MHz. It also integrates an Audio
clock phase locked loop ideal for the 8.192MHz,
11.2896MHz and 12.288MHz audio outputs, starting
from an audio reference clock. Its very high pull
range makes it ideal for Digital Video applications,
allowing users to save board space and cost.
BLOCK DIAGRAM
Note: * Pins reserved for future DAC integration
OUTPUT RANGE
OUTPUT
VCXO
Audio
FREQUENCY RANGE
27MHz
8.192MHz – 12.288MHz
OUTPUT
TYPE
CMOS
CMOS
VCON
VARICAP
XIN
XOUT
XTAL
OSC
REF_Audio
10X
PLL
OUT_27MHz
OUT_Audio
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/17/04 Page 1