PLL502-21 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – 384MHz - 768MHz Low Phase Noise PECL VCXO (12 - 24MHz Crystal)

Preliminary PLL502-21
384MHz – 768MHz Low Phase Noise PECL VCXO (12 – 24MHz Crystal)
FEATURES
• Low phase noise output for the 384MHz to
768MHz range (-130 dBc at 10kHz offset).
• PECL output.
• 12 to 24MHz crystal input.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output Enable selector.
• Wide pull range (+/-180 ppm)
• 3.3V operation.
• Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-21 is a monolithic low jitter and low
phase noise (-130dBc/Hz @ 10kHz offset) VCXO IC
with PECL output, for 384MHz to 768MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
FXIN x 32. This makes the PLL502-21 ideal for a wide
range of applications, including 622.08MHz for
SONET.
BLOCK DIAGRAM
PIN CONFIGURATION
VDD 1
VDD 2
XIN 3
XOUT 4
OE 5
VIN 6
GND 7
GND 8
16 VDD
15 GND_BUF
14 CLKBAR
13 VDD_BUF
12 CLK
11 GND_BUF
10 GND
9 GND
FOUT = FXIN x 32
OE (Pin 5)
Output State
0 (Default)
Output enabled
1
Tri-state
Pin 5: Logical states are defined at PECL levels.
Reference
Divider
XIN
XOUT
XTAL
OSC
VARICAP
VIN
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLKBAR
CLK
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Rev 08/10/01 Page 1