PLL502-12 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – 96MHz - 200MHz Low Phase Noise LVDS VCXO (12 - 25MHz Crystals)

Preliminary PLL502-12
96MHz – 200MHz Low Phase Noise LVDS VCXO (12 – 25MHz Crystals)
FEATURES
• Low phase noise output for the 96MHz to
200MHz range (-125 dBc at 10kHz offset).
• LVDS output.
• 12 to 25MHz crystal input.
• Integrated crystal load capacitor: no external
load capacitor required.
• Output Enable selector.
• Wide pull range (min. +/-190 ppm)
• 3.3V operation.
• Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-12 is a monolithic low jitter and low
phase noise (-125dBc/Hz @ 10kHz offset) VCXO IC
with LVDS output, for 96MHz to 200MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
FXIN x 8. This makes the PLL502-12 ideal for a wide
range of applications, including 155.52MHz for
SONET.
BLOCK DIAGRAM
PIN CONFIGURATION
VDD 1
VDD 2
XIN 3
XOUT 4
OE 5
VIN 6
GND 7
GND 8
16 VDD
15 GND_BUF
14 CLKBAR
13 VDD_BUF
12 CLK
11 GND_BUF
10 GND
9 GND
FOUT = FXIN x 8
OE (Pin 5)
0
1 (Default)
Output State
Tri-state
Output enabled
Reference
Divider
XIN
XOUT
XTAL
OSC
VARICAP
VIN
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
CLKBAR
CLK
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Rev 7/15/02 Page 1