PLL502-05 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise VCXO (12MHz to 25MHz)

PLL502-05
Low Phase Noise VCXO (12MHz to 25MHz)
FEATURES
• Low phase noise VCXO output for the 12MHz to
25MHz range (-135 dBc at 10kHz offset).
• CMOS output.
• 12 to 25MHz crystal input.
• Integrated variable capacitors.
• Wide pull range (+/- 300 ppm).
• Low jitter (RMS): 2.2ps period.
• 2.5 or 3.3V operation voltage.
• Available in 8-Pin SOIC.
PIN CONFIGURATION
XOUT 1
N/C 2
VCON 3
GND 4
8 XIN
7 OE^
6 VDD
5 CLK
Note: ^ denotes internal pull up
DESCRIPTION
The PLL502-05 is a low cost, high performance and
low phase noise VCXO, providing less than -135dBc
at 10 kHz offset in the 12MHz to 25MHz operating
range. The very low jitter (2.2ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 25MHz (fundamental resonant
mode).
BLOCK DIAGRAM
OUTPUT RANGE
MULTIPLIER
No PLL
FREQUENCY
RANGE
12 - 25MHz
OUTPUT
BUFFER
CMOS
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
XIN
XOUT
XTAL
OSC
VARICAP
VCON
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/17/04 Page 1