PLL502-04 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise VCXO (96MHz to 200MHz)

PLL502-04
Low Phase Noise VCXO (96MHz to 200MHz)
FEATURES
• VCXO output for the 96MHz to 200MHz range
• Low phase noise.
• CMOS output.
• 12 to 25MHz crystal input.
• Integrated variable capacitors.
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• Wide pull range (+/- 250 ppm).
• Low jitter (RMS): 4ps period.
• 3.3V operation.
• Available in 8-Pin SOIC.
DESCRIPTION
The PLL502-04 is a low cost, high performance and
low phase noise VCXO for the 96 to 200MHz range.
The very low jitter (4ps RMS period jitter at
155.52MHz) makes this chip ideal for applications
requiring voltage controlled frequency sources in
CMOS. Input crystal can range from 12 to 25MHz
(fundamental resonant mode).
BLOCK DIAGRAM
PIN CONFIGURATION
XOUT 1
N/C 2
VCON 3
GND 4
8 XIN
7 OE^
6 VDD
5 CLK
Note: ^ denotes internal pull up
OUTPUT RANGE
MULTIPLIER
X8
FREQUENCY
RANGE
96 - 200MHz
OUTPUT
BUFFER
CMOS
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
XIN
XOUT
XTAL
OSC
VARICAP
VCON
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/17/04 Page 1