PLL502-03 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Low Phase Noise VCXO (48MHz to 100MHz)

PLL502-03
Low Phase Noise VCXO (48MHz to 100MHz)
FEATURES
• VCXO output for the 48MHz to 100MHz range
• Low phase noise (-130 dBc @ 10kHz offset at
48MHz).
• CMOS output.
• 12 to 25MHz crystal input.
• Integrated variable capacitors.
• Selectable High Drive (30mA) or Standard Drive
(10mA) output.
• Wide pull range (+/- 250 ppm).
• Low jitter (RMS): 3.5ps period.
• 3.3V operation.
• Available in 8-Pin SOIC.
DESCRIPTION
The PLL502-03 is a low cost, high performance and
low phase noise VCXO for the 48 to 100MHz range,
providing less than -130dBc at 10kHz offset at
48MHz. The very low jitter (3.5ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 25MHz (fundamental resonant
mode).
BLOCK DIAGRAM
PIN CONFIGURATION
XOUT 1
N/C 2
VCON 3
GND 4
8 XIN
7 OE^
6 VDD
5 CLK
Note: ^ denotes internal pull up
OUTPUT RANGE
MULTIPLIER
X4
FREQUENCY
RANGE
48 - 100MHz
OUTPUT
BUFFER
CMOS
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
XIN
XOUT
XTAL
OSC
VARICAP
VCON
Loop
Filter
VCO
OE
CLK
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/17/04 Page 1