PLL502-01 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise VCXO (24MHz to 50MHz)

PLL502-01 Preliminary for proposal
Low Phase Noise VCXO (24MHz to 50MHz)
FEATURES
• Low phase noise VCXO output for the 24MHz to
50MHz range (-130 dBc at 10kHz offset).
• CMOS output.
• 12 to 25MHz crystal input.
• Integrated variable capacitors.
• Selectable High Drive (36mA drive capability at
TTL level) or Standard Drive (12mA drive capa-
bility at TTL) output.
• Wide pull range (+/- 250 ppm).
• Low jitter (RMS): 10ps period.
• 3.3V operation.
• Available in 8-Pin TSSOP or SOIC.
DESCRIPTIONS
The PLL502-01 is a low cost, high performance and
low phase noise VCXO, providing less than -130dBc
at 10kHz offset in the 24MHz to 50MHz operating
range. The very low jitter (10 ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 25MHz (fundamental resonant
mode).
BLOCK DIAGRAM
PIN CONFIGURATION
XOUT 1
N/C 2
VIN 3
GND 4
8 XIN
7 OE
6 VDD
5 CLK
OUTPUT RANGE
MULTIPLIER
x2
FREQUENCY
RANGE
24 - 50MHz
OUTPUT
BUFFER
CMOS
Reference
Divider
XIN
XOUT
XTAL
OSC
VARICAP
VIN
VCO
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
OE
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
CLK
Rev 4/01/02 Page 1