PLL500-37 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise VCXO (36MHz to 130MHz)

P (Preliminary) LL500-37
Low Phase Noise VCXO (36MHz to 130MHz)
FEATURES
• VCXO output for the 36MHz to 130MHz range
• Low phase noise (-148 dBc @ 10kHz offset at
77.76MHz).
• CMOS output with OE tri-state control.
• 36 to 130MHz fundamental crystal input.
• Integrated high linearity variable capacitors.
• 8mA drive capability at TTL output.
• +/- 150 ppm pull range, max 5% linearity.
• Low jitter (RMS): 2.5ps period jitter.
• Single 2.5V ±10% or 3.3V ±10 power supply.
• Operating temperature range from -40°C to +85°C
• Available in Die or Wafer form.
PIN AND PAD CONFIGURATION
32 mil
(812,986)
1 XIN
8
XOUT
2 OE^
3 VCON
4 GND
OE^ 7
VDD 6
CLK 5
Y (0,0)
X
Note: ^ denotes pull-up resistor
DESCRIPTION
The PLL500-37 is a low cost, high performance and
low phase noise VCXO for the 36 to 130MHz range,
providing less than -148dBc at 10kHz offset at
77.76MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 36 to 130MHz (fundamental resonant
mode).
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
12 mil
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 03/01/06 Page 1