PLL500-17B Datasheet, PDF (1/5 Pages) PhaseLink Corporation – Low Phase Noise VCXO (17MHz to 36MHz)

PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
• VCXO output for the 17MHz to 130MHz range
- PLL500-17B: 17MHz to 36MHz
- PLL500-27B: 27MHz to 65MHz
- PLL500-37B: 65MHz to 130MHz
• Low phase noise (-142 dBc @ 10kHz offset).
• CMOS output with OE tri-state control.
• Selectable output drive (Standard or High drive).
- Standard: 8mA drive capability at TTL level.
- High: 24mA drive capability at TTL level.
• Fundamental crystal input.
• Integrated high linearity variable capacitors.
• +/- 150 ppm pull range, max 5% linearity.
• Low jitter (RMS): 2.5ps period jitter.
• 2.5 to 3.3V operation.
• Available in 8-Pin SOIC or DIE.
DESCRIPTION
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc at 10kHz offset. The very low jitter (2.5
ps RMS period jitter) makes these chips ideal for
applications requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
FREQUENCY RANGE
PART #
PLL500-17B
PLL500-27B
PLL500-37B
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
PIN CONFIGURATION
XIN 1
OE^ 2
VIN 3
GND 4
8 XOUT
7 DS^
6 VDD*
5 CLK
^: Denotes internal Pull-up
DIE PAD LAYOUT
32 mil
(812,986)
1 XIN
8
XOUT
DRIVSEL^ 7
2 OE^
VDD 6
3 VCON
CLK 5
4 GND
DIE ID:PLL500-17B: C500A0505-05P
PLL500-27B: C500A0505-05Q
Y ^(0,0)
PLL500-37B: C500A0505-05R
X _{Note: ^ denotes internal pull up}
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
39 x 32 mil
GND
80 micron x 80 micron
10 mil
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/21/05 Page 1