PLL130-09 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – High Speed Translator Buffer to LVDS

PLL130-09
High Speed Translator Buffer to LVDS
FEATURES
• Differential LVDS output
• Single AC coupled input (min. 100mV swing).
• Input range from DC to 1.0 GHz.
• 2.5V to 3.3V operation.
• Available in 8-Pin SOIC or 3x3mm QFN.
DESCRIPTION
The PLL130-09 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 1.0GHz. It provides a pair of
differential LVDS output. Any input signal with at
least 100mV swing can be used as reference
signal. This chip is ideal for conversion from sine
wave, TTL, CMOS, or PECL to LVDS.
PIN CONFIGURATION
(TOP VIEW)
GND 1
REF_IN 2
GND 3
LVDS 4
8 VDD
7 GND
6 LVDS_BAR
5 VDD
GND
GND
GND
OE^
12
13
11 10
9
8
14 _PLL130-09 7
15
6
16
5
123 4
LVDS_BAR
VDD
LVDS
GND
Note: ^ denotes internal pull up
BLOCK DIAGRAM
REF_IN
Input
Amplifier
LVDS_BAR
LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/09/04 Page 1