PLL130-08 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – High Speed Translator Buffer to PECL

PLL130-08
High Speed Translator Buffer to PECL
FEATURES
• Differential PECL output
• Single AC coupled input (min. 100mV swing).
• Input range from DC to 1.0 GHz.
• 2.5V to 3.3V operation.
• Available in 8-Pin SOIC or 3x3mm QFN.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
GND 1
REF_IN 2
GND 3
PECL 4
8 VDD
7 GND
6 PECL_BAR
5 VDD
The PLL130-08 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 1.0GHz. It provides a pair of
differential PECL output. Any input signal with at
least 100mV swing can be used as reference
signal. This chip is ideal for conversion from sine
wave, TTL, CMOS, or LVDS to PECL.
GND
GND
GND
OE^
12 11 10
13
9
8
14 _PLL130-08 7
15
6
16
5
123 4
PECL_BAR
VDD
PECL
GND
BLOCK DIAGRAM
Note: ^ denotes internal pull up
REF_IN
Input
Amplifier
PECL_BAR
PECL
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/09/04 Page 1