PLL130-07 Datasheet, PDF (1/5 Pages) PhaseLink Corporation – High Speed Translator Buffer to CMOS (Selectable Drive)

PLL130-07
High Speed Translator Buffer to CMOS (Selectable Drive)
FEATURES
• CMOS output
• Selectable Drive capability (15pF or 30pF
output load).
• Single AC coupled input (min. 100mV swing).
• Input range from DC to 200 MHz.
• 2.5V to 3.3V operation.
• Available in 8-Pin SOIC and 3x3mm QFN.
DESCRIPTION
The PLL130-07 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 200MHz. It provides CMOS
output with 15pF output load drive capability.
Any input signal with at least 100mV swing can
be used as reference signal. This chip is ideal
for conversion from sine wave to CMOS.
PIN CONFIGURATION
(TOP VIEW)
GND 1
REF_IN 2
GND 3
VDD 4
8 DRIV_SEL^
7 VDD
6 GND
5 CLK_OUT
DRIV_SEL^
GND
GND
OE^
12 11 10
13
9
8
14
PLL130-07
7
15
6
16
5
123 4
CLK_OUT
VDD
N/C
GND
BLOCK DIAGRAM
Note: ^ denotes internal pull up
REF_IN
Input
Amplifier
CLK_OUT
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/09/04 Page 1