PLL103-11 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Skew Buffers

FEATURES
• Generates 13 copies of High-speed clock inputs.
• Supports up to three SDRAM DIMMS synchronous
clocks.
• Supports 2-wire I2C serial bus interface with
readback.
• 50% duty cycle with low jitter.
• Less than 5ns delay.
• Skew between any outputs is less than 250 ps.
• Tri-state pin for testing.
• Frequency up to 150 MHz.
• 3.0V-3.7V Supply range.
• Available in 28-pin 300mil SOIC package.
BLOCK DIAGRAM
PLL103-11
Low Skew Buffers
PIN CONFIGURATION
VDD 1
SDRAM0 2
SDRAM1 3
GND 4
VDD 5
SDRAM2 6
SDRAM3 7
GND 8
BUF_IN 9
SDRAM4 10
SDRAM5 11
SDRAM12 12
VDD1 13
SDATA 14
28 VDD
27 SDRAM11
26 SDRAM10
25 GND
24 VDD
23 SDRAM9
22 SDRAM8
21 GND
20 VDD
19 SDRAM7
18 SDRAM6
17 GND
16 GND1
15 SCLK
SDATA
SCLK
I2C
Control
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
POWER GROUP
• VDD: SDRAM (0:12)
• VDD1: I2C Circuitry
GROUND GROUP
• GND: SDRAM (0:12)
• GND1: I2C Circuitry
KEY SPECIFICATIONS
• BUF_IN to SDRAM outputs Delay: 1 ~ 5 ns.
• Output Slew: ≥1.5 V/ns.
• Output Skew: ±250 ps.
• Output Duty Cycle: 50% ± 5%.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 11/07/00 Page 1