PLL103-07 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – 2 DIMM DDR Fanout Buffer

FEATURES
• Generates 12-output buffers from one input.
• Supports VIA Pro266 DDR chipset.
• Supports up to 2 DDR DIMMS.
• Supports up to 400MHz DDR, SDRAMS.
• One additional output for feedback.
• 6 differential clock distribution.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Available in 28-pin SSOP.
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
FBOUT
Preliminary PLL103-07
2 DIMM DDR Fanout Buffer
PIN CONFIGURATION
FBOUT 1
GND 2
DDRT0 3
DDRC0 4
VDD2.5 5
GND 6
DDRT1 7
DDRC1 8
VDD2.5 9
BUF_IN 10
GND 11
DDRT2 12
DDRC2 13
VDD2.5 14
Note: #: Active Low
28 GND
27 DDRT5
26 DDRC5
25 VDD2.5
24 GND
23 DDRT4
22 DDRC4
21 VDD2.5
20 GND
19 DDRT3
18 DDRC3
17 VDD2.5
16 SCLK
15 SDATA
DESCRIPTIONS
The PLL103-07 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 12 outputs. These outputs can be
configured to support 2 DDR DIMMs. The PLL103-07
can be used in conjunction with the PLL202-04 or
similar clock synthesizer for the VIA Pro 266 chipset.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 01/03/01 Page 1