PLL103-06 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

Preliminary PLL103-06
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS
FEATURES
• Generates 12-output buffers from one input.
• Supports up to 2 DDR DIMMS or 3 SDRAM
DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V or 3.3V Supply range.
• Enhanced DDR and SDRAM Output Drive
selected by I2C.
• Available in 28 pin SSOP.
BLOCK DIAGRAM
SDATA
SCLK
PD#
I2C
Control
BUF_IN
SEL_DDR
DDR0T_SDRAM0
DDR0C_SDRAM1
DDR1T_SDRAM2
DDR1C_SDRAM3
DDR2T_SDRAM4
DDR2C_SDRAM5
DDR3T_SDRAM6
DDR3C_SDRAM7
DDR4T_SDRAM8
DDR4C_SDRAM9
DDR5T_SDRAM10
DDR5C_SDRAM11
FBOUT
PIN CONFIGURATION
FBOUT 1
PD# 2
DDR0T_SDRAM0 3
DDR0C_SDRAM1 4
VDD3.3_2.5 5
GND 6
DDR1T_SDRAM2 7
DDR1C_SDRAM3 8
VDD3.3_2.5 9
BUF_IN 10
GND 11
DDR2T_SDRAM4 12
DDR2C_SDRAM5 13
VDD3.3_2.5 14
Note: #: Active Low
28 SEL_DDR
27 DDR5T_SDRAM10
26 DDR5C_SDRAM11
25 VDD3.3_2.5
24 GND
23 DDR4T_SDRAM8
22 DDR4C_SDRAM9
21 VDD3.3_2.5
20 GND
19 DDR3T_SDRAM6
18 DDR3C_SDRAM7
17 GND
16 SCLK
15 SDATA
DESCRIPTIONS
The PLL103-06 is designed as a 3.3V/2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 12 outputs. These outputs can be
configured to support 3 unbuffered standard SDR
(Single Data Rate) DIMMS and 2 DDR DIMMS. The
PLL103-06 can be used in conjunction with the
PLL202-04 or similar clock synthesizer for the VIA
Pro 266 chipset.
The PLL103-06 also has an I2C interface, which can
enable or disable each output clock. When power up,
all output clocks are enabled (has internal pull up).
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 12/20/00 Page 1