PLL103-02 Datasheet, PDF (1/6 Pages) List of Unclassifed Manufacturers – DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
FEATURES
• Generates 24 output buffers from one input.
• Supports up to four DDR DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Enhanced DDR Output Drive selected by I2C.
• Available in 48 pin SSOP.
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
PD#
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PIN CONFIGURATION
FBOUT
1
VDD2.5
2
GND
3
DDR0T
4
DDR0C
5
DDR1T
6
DDR1C
7
VDD2.5
8
GND
9
DDR2T
10
DDR2C
11
VDD2.5
12
BUF_IN
13
GND
14
DDR3T
15
DDR3C
16
VDD2.5
17
GND
18
DDR4T
19
DDR4C
20
DDR5T
21
DDR5C
22
VDD2.5
23
SDATA
24
Note: #: Active Low
48
N/C
47
VDD2.5
46
GND
45
DDR11T
44
DDR11C
43
DDR10T
42
DDR10C
41
VDD2.5
40
GND
39
DDR9T
38
DDR9C
37
VDD2.5
36
PD#
35
GND
34
DDR8T
33
DDR8C
32
VDD2.5
31
GND
30
DDR7T
29
DDR7C
28
DDR6T
27
DDR6C
26
GND
25
SCLK
DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 can be used in conjunction with a
clock synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When powered
up, all output clocks are enabled (have internal pull
ups).
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/09/04 Page 1