PLL103-01 Datasheet, PDF (1/7 Pages) PhaseLink Corporation – Low Skew Buffers

FEATURES
• Generate 18 copies of High-speed clock inputs.
• Supports up to four SDRAM DIMMS synchronous
clocks.
• Supports 2-wire I2C serial bus interface with
readback.
• 50% duty cycle with low jitter.
• Less than 5ns delay.
• Skew between any outputs is less than 250 ps.
• Tri-state pin for testing.
• Frequency up to 133 MHZ.
• 3.0V-3.7V Supply range.
• 48-pin SSOP package.
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
PLL103-01
Low Skew Buffers
PIN CONFIGURATION
N/C 1
N/C 2
VDD 3
SDRAM0 4
SDRAM1 5
GND 6
VDD 7
SDRAM2 8
SDRAM3 9
GND
10
BUF_IN
11
VDD
12
SDRAM4 13
SDRAM5 14
GND 15
VDD
16
SDRAM6 17
SDRAM7 18
GND 19
VDD
20
SDRAM16 21
GND
22
VDD1
23
SDATA 24
Note: ^: pull up
48
N/C
47
N/C
46
VDD
45 SDRAM15
44 SDRAM14
43
GND
42
VDD
41 SDRAM13
40 SDRAM12
39
GND
38
OE^
37
VDD
36 SDRAM11
35 SDRAM10
34 GND
33
VDD
32 SDRAM9
31 SDRAM8
30
GND
29
VDD
28 SDRAM17
27
GND
26
GND1
25 SCLK
POWER GROUP
• VDD: SDRAM( 0:17 )
• VDD1: I2C Circuitry
GROUND GROUP
• GND: SDRAM( 0:17 )
• GND1: I2C Circuitry
KEY SPECIFICATIONS
• BUFIN to SDRAM outputs Delay: 1 ~ 5 ns.
• Output Slew: ≥1.5 V/ns.
• Output Skew: ±250 ps.
• Output Duty Cycle: 50% ± 5%.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Rev 03/08/00 Page 1