PLL102-108 Datasheet, PDF (1/10 Pages) PhaseLink Corporation – Programmable DDR Zero Delay Clock Driver

PLL102-108
Programmable DDR Zero Delay Clock Driver
FEATURES
• PLL clock distribution optimized for Double Data
Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of ten
differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and
CLK[T/C] from –0.8ns to +3.1ns by programming
CLKINT and FBOUT skew channel, or from –1.1ns to
+3.5ns if additional DDR skew channels are enabled.
• Four independent programmable DDR skew chan-
nels from –0.3ns to +0.4ns with step size ±100ps.
• Support 2-wire I2C serial bus interface.
• 2.5V Operating Voltage.
• Available in 48-Pin 300mil SSOP.
DESCRIPTIONS
The PLL102-108 is a zero delay buffer that distributes
a single-ended clock input to ten pairs of differential
clock outputs and one feedback clock output. Output
signal duty cycles are adjusted to 50%, independent of
the duty cycle at CLK_INT. The PLL can be bypassed
for test purposes by strapping AVdd to ground.
BLOCK DIAGRAM
PIN CONFIGURATION
GND 1
CLKC0 2
CLKT0 3
VDD 4
CLKT1 5
CLKC1 6
GND 7
GND 8
CLKC2 9
CLKT2 10
VDD 11
SCLK 12
CLK_INT 13
N/C 14
VDD 15
AVDD 16
AGND 17
GND 18
CLKC3 19
CLKT3 20
VDD 21
CLKT4 22
CLKC4 23
GND 24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 SDATA
36 N/C
35 FB_INT
34 VDD
33 FB_OUTT
32 N/C
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
AV _DD
CLK_INT
Programmable
Delay Channel
(0~2.5ns)
+170ps step
FB_INT
AV DD
Control
Logic
PLL
Programmable
Skew Channel
-600~+800ps
±200ps step
-300~+400ps
±100ps step
-300~+400ps
±100ps step
-300~+400ps
±100ps step
-300~+400ps
±100ps step
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
CLKT5
CLKC5
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
CLKT6
CLKC6
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Rev 03/29/02 Page 1