LV7X45DEW Datasheet, PDF (6/9 Pages) Pletronics, Inc. – LVDS Clock Oscillators

Mechanical:
LV76D / LV78D Series 2.5 V
LVDS Clock Oscillators
January 2008
Label:
laser marked lettering
FR4 PCB Base:
Solder masked
All via holes tented on bottom
Copper Clad 670 µinch (17 µm)
Nickel plated 118 µinch (3 µm)
Gold plated 0.8 µinch (0.02 µm)
Typical thicknesses
Pin 3 Ground plane is typical
Not to scale
Inches
mm
B 0.356 +_0.005
C 0.126 +_0.005
D 0.324 +_0.005
F¹ 0.050
G¹ 0.040
9.04 +_0.13
3.21 +_0.13
8.23 +_0.13
1.27
1.02
H¹ 0.059
1.50
I¹ 0.020
0.51
J¹ 0.040
1.02
K¹ 0.100
2.54
L¹ 0.062
1.57
Pad Function
76 78
1 2 No connect
Note
There is no internal connection to this pad
2 1 Output
Enable/Disable
3
Ground (GND)
4
Output
5
Output*
6
Supply Voltage
(V_CC)
When this pad is not connected the oscillator shall operate.
When this pad is <0.30 volts, the output will be inhibited (high impedance state.)
Recommend connecting this pad to V_CC if the oscillator is to be always on.
The outputs must be terminated, 100 ohms between the outputs is the ideal
termination.
Recommend connecting appropriate power supply bypass capacitors as close as
possible.
Layout and application information
Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both
input pads (see LV76D for E/D on pad 1)
For Optimum Jitter Performance, Pletronics recommends:
• a ground plane under the device
• no large transient signals (both current and voltage) should be routed under the device
• do not layout near a large magnetic field such as a high frequency switching power supply
www.pletronics.com
425-776-1880
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