PAS202BCB Datasheet, PDF (8/15 Pages) Pixart Imaging Inc. – PAS202BCB SINGLE-CHIP CMOS VGA COLOR DIGITAL IMAGE SENSOR PAS202BBB SINGLE-CHIP CMOS VGA B&W DIGITAL IMAGE SENSOR

PixArt Imaging Inc.
PAS202BCB/PAS202BBB
CMOS Image Sensor IC
SDA
SCL
DATA
STABLE
DATA
CHANGE
ALLOWED
Fig 4.2 Valid Data
4.2 Data Transfer Format
4.2.1 Master transmits data to slave (write cycle)
§ S : Start
§ A : Acknowledge by slave
§ P : Stop
§ RW : The LSB of 1^ST byte to decide whether current cycle is read or write cycle.
RW=1 read cycle, RW=0 write cycle.
§ SUBADDRESS : The address values of PAS202BCB/PAS202BBB internal control registers
(Please refer to PAS202BCB/PAS202BBB register description)
1ST BYTE
S
SLAVE ID (7 BIT)
RW A
2ND BYTE
SUBADDRESS (8 BIT)
n BYTEs + A
A DATA A DATA
A
P
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1^st byte data that are combined
slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCB/PAS202BBB) issues
acknowledgment, the master places 2^nd byte (sub-address) data on SDA line. Again follow the
PAS202BCB/PAS202BBB acknowledgment, the master places the 8 bits data on SDA line and transmit to
PAS202BCB/PAS202BBB control register (address was assigned by 2^nd byte). After
PAS202BCB/PAS202BBB issue acknowledgment, the master can generate a stop condition to end of this
write cycle. In the condition of multi-byte write, the PAS202BCB/PAS202BBB sub-address is automatically
increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control
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PixArt Imaging Inc.
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V2.0, May 2002