PAC7366 Datasheet, PDF (7/23 Pages) Pixart Imaging Inc. – NTSC/PAL DIGITAL IMAGE SOC

PAC7366
I²C^TM Bus Timing
NTSC/PAL Digital Image SOC
Fig.3.5 Definition of timing for F/S-mode devices on the I2C-bus.
I²C^TM Bus Timing Specification
Parameter
Symbol
SCL clock frequency.
Hold time ( repeated ) Start condition.
After this period, the first clock pulse is generated.
Low period of the SCL clock.
High period of the SCL clock.
Set-up time for a repeated START condition.
Data hold time. For I2C-bus device.
Data set-up time.
Rise time of both SDA and SCL signals.
f_scl
t_HD:STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_r
Fall time of both SDA and SCL signals.
t_f
Set-up time for STOP condition.
Bus free time between a STOP and START.
Capacitive load for each bus line.
Noise margin at LOW level for each connected device.
( Including hysteresis )
Noise margin at HIGH level for each connected device.
( including hysteresis )
Note: It depends on the “high” period time of SCL.
t_SU;STO
t_BUF
C_b
V_nL
V_nH
Standard Mode
Min. Max
10
400
4.0
-
4.7
-
0.75
-
4.7
-
0
3.45
250
-
30 N.D.
30 N.D.
4.0
-
4.7
-
1
15
0.1
VDD
-
0.2
VDD
-
Unit
KHz
μs
μs
μs
μs
μs
ns
ns
( notel )
ns
( notel )
μs
μs
pF
V
V
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PixArt Imaging Inc.
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V1.10
7
Dec. 2012