PAN3401 Datasheet, PDF (11/15 Pages) Pixart Imaging Inc. – PS/2 OPTICAL MOUSE SINGLE CHIP

PixArt Imaging Inc.
PAN3401
PS/2 Optical Mouse Single Chip
8. PS/2 Data Transmission
8.1 Mouse Send Data Out to Host
When the mouse is ready to transmit data, it must first check for mouse “inhibit” or system “request to send”
status on clock and data lines. If CLK is low (inhibit status), data shall be continuously updated in the mouse and
no transmissions shall be started. If CLK is high and DATA is low (request-to-send), data is updated. Data is
received from the system and no transmission are started by the PAN3401 until CLK and DATA both high.
If CLK and DATA are both high, the transmission is ready. DATA is valid prior to the falling edge of CLK and
beyond the rising edge of CLK. During transmission, the PAN3401 checks for line contention by checking for
an inactive level on CLK at intervals not to exceed 100 microseconds. Contention occurs when the system
lowers CLK to inhibit the PAN3401 output after the PAN3401 has started a transmission. If this occurs prior to
the rising edge of the tenth clock (parity bit), the PAN3401 internally stores the data package in its buffer and
return DATA and CLK to an active level. If the contention does not occur by the tenth clock, the transmission is
complete.
Following a transmission, the system can inhibit the PAN3401 by holding CLK low until it can service the input
or until the system receives a request to send a response if necessary.
CLK
Tsca
1^st
CLK
2^nd
CLK
Tsci
Tsdc
Tscd
10^th
CLK
11^th
CLK
………
Tpi
DATA
Start bit
……… …
Bit0 - Bit7
Parity bit
Stop bit
………
Figure 7. Mouse Send Data Out to Host
8.2 Mouse Receive Data from Host
System first check to see if the PAN3401 is transmitting data. If the PAN3401 is transmitting, the system can
override the output forcing CLK to an inactive level prior to the tenth clock. If the PAN3401 transmission is
beyond the tenth clock, the system receives the data. If the PAN3401 is not transmitting or if the system chooses
to override the output, the system forces CLK to an inactive level for a period of not less than 100 microseconds
while preparing for output. When the system is ready to output “0” start bit, it allows CLK to go to active level.
If “request-to-send” is detected, the PAN3401 clocks in 11 bits. Following the tenth clock, the PAN3401 checks
for an active level on the DATA line, and if found, force DATA low (line control bit), and clock once more. If
occurs framing error, the PAN3401 continue to clock until DATA is high, then clock the line control bit and
request a resend.
For each system command or data transmission to the PAN3401 that requires a response, the system must wait
for the PAN3401 to response before sending its next output.
CLK
DATA
Tmca
Inhibit
1^st
CLK
2 ^nd
CLK
9 ^th
CLK
10 ^th
CLK
11 ^th
CLK
……
Tmci
Tmdc
Tmlc
Start bit
………
…
…
Bit0 - Bit7
Parity bit
Stop
Line
bit control bit
Figure 8. Mouse Receive Data from Host
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PixArt Imaging Inc.
E-mail: [e-mail]
V1.3, Mar. 2008