PCA5007 Datasheet, PDF (99/112 Pages) NXP Semiconductors – Pager baseband controller

Philips Semiconductors
Pager baseband controller
Product specification
PCA5007
Table 65 Entering the parallel programming mode; note 1
PINS PSEN, ALE AND
EA
000
000
000
RESETIN
1
0
0
RESOUT
0
0
0→1
PORT 0
XX
XX
XX
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ0
ZZ1
Note
1. Z = pin is output.
0
1
02
0
1
30
0
1
00
0
1
00
0
1
75
0
1
87
0
1
01
0
1
01
0
1
XX
DESCRIPTION
reset
259 or more slow clocks at XTL1
prepare parallel programming mode, enter
external access mode, now clocks must be
provided on TCLK
LJMP 3000H
force P2 to 30H
discard fetch cycle
MOV PCON, 01H
make microcontroller idle
discard fetch cycle
parallel programming mode active
width
3T
ALE
PSEN
ALE, PSEN cycle
4T 5T 6T 1T 2T 3T 4T 5T 6T .... nT
0T
tCE
instruction execution cycle
variable
execute time
T
P0
DATA input
P2
AH driven
AL
driven
DATA input
AH driven
MGR165
T is the half period of the clock
signal supplied to TCLK.
The minimum duration of one
cycle is 6T. It can be extended by
increments of [0 to n]T if the
execution of an instruction needs
more time (dependant of V_DD, T,
temperature, opcode).
Execution of an opcode goes in
parallel with the external access
cycle for the next sequential byte.
Eventually an already fetched
byte is discarded depending on
the executed instruction (e.g. any
jump or return).
Fig.62 External access timing for programming mode entry.
1998 Oct 07
99