TEA1721AT Datasheet, PDF (9/14 Pages) NXP Semiconductors – Ultra-low standby SMPS controller with integrated power switch

NXP Semiconductors
TEA1721AT
Ultra-low standby SMPS controller with integrated power switch
Table 5. Characteristics …continued
V_CC = 20 V; V_FB = 0 V; R_source = 1.5 Ω; T_j-switch = 25 °C; T_j-controller = 25 °C; all voltages referenced to GND,
positive currents flow into the IC, unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Unit
f_osc-high
oscillator frequency
High
maximum switching frequency in CV
and CC mode, without jitter
48 50.5 53 kHz
f_osc-low
oscillator frequency
Low
minimum switching frequency in CV
and CC mode, without jitter. Switching
frequency in CVB mode
21 22.5 24 kHz
f_sweep
jitter sweep frequency
δ_max
maximum duty cycle
Power switch (Pin: DRAIN)
In current source operation
150 200 250 Hz
72 75 78 %
I_drain(off)
I_{drain(start-up)}
R_DSon
off-state drain current
start-up drain current
drain-source on-state
resistance
V_DRAIN = 325 V
V_CC = 0 V
T_j = 25 °C; I_ds = 30 mA
-
1
-
µA
-
1
-
mA
-
13.2 -
Ω
V_(BR)DS
drain-source
breakdown voltage
700 -
-
V
Peak current comparator (Pin: SOURCE)
t_d(ocp)
overcurrent protection dV/dt = 0.2 V/µs
delay time
-
100 -
ns
t_leb
leading edge blanking
time
290 325 360 ns
V_{ref-peak-high}
reference voltage ,
high peak voltage
in CVF and CCF modes
0.525 0.555 0.585 V
V_ref-peak-low
reference voltage , low in CVB mode
peak voltage
0.085 0.1 0.115 V
V_{ref-0 V}
reference voltage at
start-up or 0 V
feedback voltage
in CCC mode with V_FBS = 0 V
0.18 0.21 0.24 V
TEA1721AT
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 24 January 2012
© NXP B.V. 2012. All rights reserved.
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