TDA8761A Datasheet, PDF (9/24 Pages) NXP Semiconductors – 9-bit analog-to-digital converter for digital video

Philips Semiconductors
9-bit analog-to-digital converter
for digital video
Product specification
TDA8761A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (f_clk = 30 MHz; C_L = 15 pF); see Fig.4; note 11
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
C_L
digital output load
V_CCO = 4.75 V
V_CCO = 3.15 V
−
3
−
ns
4
−
−
ns
−
10
13
ns
−
12
15
ns
−
−
15
pF
3-state output delay times; see Fig.5
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
5.5
8.5
ns
−
12
15
ns
−
19
24
ns
−
12
15
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) V_osB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V_RB) at T_amb = 25 °C.
b) V_osT (voltage offset TOP) is the difference between V_RT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at T_amb = 25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins V_RB and V_RT via offset resistors R_OB and R_OT as shown in Fig.3.
a) The current flowing into the resistor ladder is I_L = _R-----O---V-_B---^R-₊---^T--R--^–---_L--V--₊--^R---R-^B---_O----_T- and the full-scale input range at the converter,
to cover code 0 to code 511, is V_I = R_L × I_L = _R-----O----_B----₊-----RR-----^LL----₊-----R----_O----_T- × (V_RT – V_RB ) = 0˙.852 × (V _RT – V_RB )
b) Since R_L, R_OB and R_OT have similar behaviour with respect to process and temperature variation, the ratio
R-----_O^----_B^----+^{-----RR-----LL----}+^-----R----_O^----_T^{- will be kept reasonably constant from device to device. Consequently variation of the output}
codes at a given input voltage depends mainly on the difference V_RT − V_RB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4. f_i = 10 MHz and f_clk = 30 MHz; f_i = 8 MHz and f_clk = 20 MHz.
5. GER = --⁽--V----⁵---¹--¹----^–--V---V-_i-₍--_p0---_-⁾-_p---₎^–-----V----ⁱ-⁽--^p--^---^p--⁾ × 100
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
1998 Nov 03
9