TDA8417 Datasheet, PDF (9/20 Pages) NXP Semiconductors – TV and VTR stereo/dual sound processor with integrated filters and I2C-bus control

Philips Semiconductors
TV and VTR stereo/dual sound processor
with integrated filters and I²C-bus control
Preliminary specification
TDA8417
Control ports
The general purpose control ports C1 and C2 can be set to LOW, HIGH or high impedance via the I²C-bus.
I²C-bus receiver and data handling
Bus specification
The TDA8417 is controlled, via the bidirectional 2-line I²C-bus, by a microcomputer. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer
may be initiated only when the bus is not busy.
When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock.
The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and
hold times are specified in the CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as the stop condition (P). The bus receiver will
be reset on the reception of a start condition. The bus is considered to be busy after the start condition. The bus is
considered to be free again after a stop condition.
The I²C-BUS PROTOCOL OF THE TDA8417
The TDA8417 is controlled by a microcomputer and can be written to or read from via the I²C-bus.
The first byte is the address and determines whether the TDA8417 is to be read from (status register) or written to (switch
register or mute and port control register).
Where:
S = start bit
A = acknowledge bit
September 1989
Read from (TDA8417 is a slave transmitter)
Write to (TDA8417 is a slave receiver)
Fig.4 Address byte.
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