TDA8261TW Datasheet, PDF (9/22 Pages) NXP Semiconductors – Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer

Philips Semiconductors
Satellite Zero-IF QPSK/8PSK
downconverter with PLL synthesizer
Product specification
TDA8261TW
I²C-bus read mode
If bit R/W = 1 the data can be read from the TDA8261TW
(see Table 7). After recognition of its slave address, the
TDA8261TW generates an acknowledge pulse and
transfers the status byte onto the SDA line (MSB first).
Data is valid on the SDA line when the SCL clock signal is
HIGH.
A second data byte can be read from the TDA8261TW if
the microcontroller generates an acknowledge on the SDA
line. End of transmission will occur if no acknowledge is
received from the microcontroller. The TDA8261TW will
then release the data line to allow the microcontroller to
generate a STOP condition.
The POR flag is set to logic 1 at power-on and when
V_CC < 2.7 V. It is reset to logic 0 when an end-of-data
condition is detected by the TDA8261TW (end of a read
sequence).
The in-lock flag FL indicates that the loop is phase-locked
when set to logic 1.
When a read sequence is started, all eight bits of the status
byte must be read.
Table 7 I²C-bus read data format
BYTE
Address
Status byte
MSB
1
1
0
POR FL⁽³⁾
X
BITS⁽¹⁾
0
0
X
X
MA1
X
MA0
X
LSB
1
X
Notes
1. X can be 1 or 0 and needs to be masked in the microcontrollers’ software; MSB is transmitted first.
2. Acknowledge bit (A).
3. FL is valid only in normal mode.
ACK⁽²⁾
A
−
POWER-ON RESET
At power-on (bit POR = 1) or when the supply voltage drops below 2.7 V, internal registers are set according to Table 8.
Table 8 Status at POR
BYTE
Programmable divider 1 (PD1)
Programmable divider 2 (PD2)
Control data 1 (CD1)
Control data 1 (CD2)
MSB
0
N7 = X
1
C1 = X
N14 = X
N6 = X
T2 = 0
C0 = X
N13 = X
N5 = X
T1 = 0
X
BITS⁽¹⁾
N12 = X N11 = X
N4 = X N3 = X
T0 = 1 R2 = X
X
X
N10 = X
N12 = X
R1 = X
X
N9 = X
N1 = X
R0 = X
X
Note
1. X = not set.
LSB
N8 = X
N0 = X
X
X
2004 Dec 02
9