PCF8548 Datasheet, PDF (9/40 Pages) NXP Semiconductors – 65 x 102 pixels matrix LCD driver

Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
PCF8548
10 ADDRESSING
The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs 3, 6, 7, 8 and 9. The DDRAM has a
matrix of 65 × 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to
X101 (1100101b) and Y0 to Y8 (1000b). Addresses outside of these ranges are not allowed. In vertical addressing mode
(V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 8), Y wraps around to 0 and
X increments to address the next column. In the horizontal addressing mode (V = 0) the X address increments after each
byte (see Fig.4). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After
the very last address (X = 101 and Y = 8) the address pointers wrap around to address X = 0 and Y = 0.
10.1 Display data RAM structure
handbook, full pagewidth
0
1
2
102 103 104
204 205 206
306 307 308
408 409 410
510 511 512
612 613 614
714 715 716
816 817 818
0
X address
0
Y address
917
8
101
MGS396
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
1999 Aug 16
9