PCF8535 Datasheet, PDF (9/52 Pages) NXP Semiconductors – 65 x 133 pixel matrix driver

Philips Semiconductors
65 × 133 pixel matrix driver
Objective specification
PCF8535
7.1 Reset
The PCF8535 has two reset modes; internal Power-on
reset or external reset. Reset initiated from either the RES
pad or the internal Power-on reset block will initialize the
chip to the following starting condition:
• Power-down mode (PD = 1)
• Horizontal addressing (V = 0); no mirror X or Y
(MX = 0 and MY = 0)
• Display blank (D = 0 and E = 0)
• Address counter X[6:0] = 0, Y[2:0] = 0 and XM₀ = 0
• Bias system BS[2:0] = 0
• Multiplex rate M[2:0] = 0 (Mux rate 1 : 17)
• Temperature control mode TC[2:0] = 0
• HV-gen control, HVE = 0 the HV generator is switched
off, PRS = 0 and S[1:0] = 00
• V_LCDOUT is equal to 0 V
• RAM data is unchanged (Note: RAM data is undefined
after power-up)
• All row and column outputs are set to V_SS (display off)
• TRS and BRS are set to zero
• Direct mode is disabled (DM = 0)
• Internal oscillator is selected, but not running (EC = 0)
• Bias current set to low current mode (IB = 0).
7.2 Power-down
During power-down all static currents are switched off (no
internal oscillator, no timing and no LCD segment drive
system) and all LCD outputs are internally connected to
V_SS. The serial bus function remains active.
7.3 LCD voltage selector
The practical value for V_OP is determined by equating
V_off(rms) with defined LCD threshold voltage (V_th), typically
when the LCD exhibits approximately 10% contrast.
7.4 Oscillator
The internal logic operation and the multi-level drive
signals of the PCF8535 are clocked by the built-in RC
oscillator. No external components are required.
7.5 Timing
The timing of the PCF8535 organizes the internal data flow
of the device. The timing also generates the LCD frame
frequency which is derived from the clock frequency
generated in the internal clock generator.
7.6 Column driver outputs
The LCD drive section includes 133 column outputs
(C0 to C132) which should be connected directly to the
LCD. The column output signals are generated in
accordance with the multiplexed row signals and with the
data in the display latch. When less than 133 columns are
required the unused column outputs should be left
open-circuit.
7.7 Row driver outputs
The LCD drive section includes 65 row outputs
(R0 to R64) which should be connected directly to the
LCD. The row output signals are generated in accordance
with the selected LCD drive mode. If lower Mux rates or
less than 65 rows are required, the unused outputs should
be left open-circuit.
1999 Aug 24
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