PCE84C486 Datasheet, PDF (9/36 Pages) NXP Semiconductors – Microcontrollers for digital auto-sync and VST TV controller applications

Philips Semiconductors
Microcontrollers for digital auto-sync and
VST TV controller applications
Objective specification
PCE84C486; PCE84C487
6 RESET
To initialize the microcontroller to a defined state a reset
operation is performed. A reset can be generated in three
ways:
• applying an external signal to the RESET pin
• via Power-on-reset circuitry
• by the Watchdog Timer.
6.1 External reset using the RESET pin
An active LOW signal from an external logic device will
reset the device. The signal must be maintained long
enough to allow V_DD to reach its f_xtal-dependent minimum
operating voltage.
6.2 Power-on-reset
A Power-on-reset can be generated using an external RC
circuit. To avoid overload of the internal diode, an external
diode should be added in parallel if C_RESET ≥ 2.2 µF.
The RC circuit is shown in Fig.5.
6.4 Reset trip level
The RESET trip voltage level for both the PCE84C486 and
PCE84C487 is masked to 1.3 V.
6.5 Reset status
• Derivative Registers reset status; see Table 8 for details
• Program Counter 00H
• Memory Bank 0
• Register Bank 0
• Stack Pointer 00H
• All interrupts disabled
• Timer/event counter 1 stopped and cleared
• Timer pre-scaler modulo-32 (PS = 0)
• Timer flag cleared
• Serial I/O interface disabled (ESO = 0) and in slave
receiver mode
• Idle and Stop mode cleared.
6.3 Watchdog Timer reset
An overflow of the Watchdog Timer will cause the device
to be reset. The operation of the Watchdog Timer is
described in Chapter 12.
handbook, halfpage
V _DD
R _RESET
( 100 kΩ)
RESET
C _RESET
V _SS
internal reset
PCA84C8XX
MLC259
Fig.5 External components for RESET pin.
1996 Feb 21
9