P3Z22V1 Datasheet, PDF (9/16 Pages) NXP Semiconductors – 3V zero power, TotalCMOS, universal PLD device

Philips Semiconductors
3V zero power, TotalCMOS™, universal PLD device
Product specification
P3Z22V10
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T_amb ≤ +70°C; 3.0 ≤ V_DD ≤ 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
LIMITS
TYP.
MAX.
UNITS
V_IL
V_IH
V_I
V_OL
V_OH
I_I
I_OZ
I_DDQ
I_DDD ¹
I_SC
Input voltage low
V_DD = 3.0V
Input voltage high
V_DD = 3.6V
2
Input clamp voltage
V_DD = 3.0V; I_IN = –18mA
Output voltage low
V_DD = 3.0V; I_OL = 8mA
Output voltage high
V_DD = 3.0V; I_OH = –4mA
2.4
Input leakage current
V_IN = 0 to V_DD
–10
V_IN = V_DD to 5.5V²
–10
3-Stated output leakage current
V_IN = 0 to V_DD
V_IN = V_DD to 5.5V²
–10
–10
Standby current
V_DD = 3.6V; T_amb = 0°C
Dynamic current
V_DD = 3.6V; T_amb = 0°C @ 1MHz
V_DD = 3.6V; T_amb = 0°C @ 50MHz
Short circuit output current
1 pin/time for no longer than 1 se-
cond
–15
0.8
V
V
–1.2
V
0.5
V
V
10
µA
10
10
µA
10
25
45
µA
.5
2
mA
10
15
mA
–100
mA
C_IN
Input pin capacitance
T_amb = 25°C; f = 1MHz
8
pF
C_CLK
Clock input capacitance
T_amb = 25°C; f = 1MHz
5
12
pF
C_I/O
I/O pin capacitance
T_amb = 25°C; f = 1MHz
10
pF
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V_DD or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T_amb ≤ +70°C; 3.0 ≤ V_DD ≤ 3.6V
SYMBOL
PARAMETER
–B
MIN.
MAX.
–D
MIN.
MAX.
UNIT
t_PD
Input or feedback to non-registered output
t_SU
Setup time from input, feedback or SP to Clock
t_CO
Clock to output
t_CF
Clock to feedback¹
t_H
Hold time
t_AR
Asynchronous Reset to registered output
t_ARW
Asynchronous Reset width
t_ARR
Asynchronous Reset recovery time
t_SPR
Synchronous Preset recovery time
t_WL
Width of Clock LOW
t_WH
Width of Clock HIGH
t_R
Input rise time
t_F
f_MAX1
Input fall time
Maximum internal frequency² (1/t_SU + t_CF)
f_MAX2
f_MAX3
Maximum external frequency¹ (1/t_SU + t_CO)
Maximum clock frequency¹ (1/t_WL + t_WH)
t_EA
Input to Output Enable
t_ER
Input to Output Disable
Capacitance
15
10
ns
4.5
3.5
ns
10
9
ns
6
4.5
ns
0
0
ns
17
17
ns
5
5
ns
6
6
ns
6
6
ns
3
3
ns
3
3
ns
20
20
ns
20
20
ns
95
125
MHz
69
80
MHz
167
167
MHz
9
9
ns
9
9
ns
C_IN
Input pin capacitance
10
10
pF
C_OUT
Output capacitance
10
10
pF
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V_DD or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
1997 Jul 18
9