TDA8766 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

Philips Semiconductors
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
Product specification
TDA8766
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
EFFECTIVE BITS; see Fig.9; note 5
EB
effective bits
f_clk = 20 MHz
f_i = 300 kHz
−
9.5 −
bits
f_i = 1 MHz
−
9.3 −
bits
f_i = 3.58 MHz
−
8.0 −
bits
Timing (f_clk = 20 MHz; C_L = 20 pF); see Fig.4; note 6
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
−
−
5
ns
5
−
−
ns
V_DDO = 4.75 V
8
12
15
ns
V_DDO = 3.15 V
8
17
20
ns
V_DDO = 2.7 V
8
21
24
ns
3-state output delay times; see Fig.5
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
14
18
ns
−
16
20
ns
−
16
20
ns
−
14
18
ns
Standby mode output delay times
t_dSTBLH
t_dSTBHL
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
−
−
200
ns
−
−
500
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 0 up to and including 1023:
a) V_osB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V_RB) at T_amb = 25 °C.
b) V_osT (voltage offset TOP) is the difference between V_RT (reference voltage TOP) and the analog input which
produces data outputs equal to 1023 at T_amb = 25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins V_RB and V_RT via offset resistors R_OB and R_OT as shown in Fig.3.
a) The current flowing into the resistor ladder is I_L = _R-----O---V-_B---^R-₊---^T--R--^–---_L--V--₊--^R---R-^B---_O----_T- and the full-scale input range at the converter,
to cover code 0 to code 1023, is V_I = R_L × I_L= -R----_O----_B----₊-----RR-----^LL----₊-----R----_O----_T- × (V_RT – V_RB) = 0.871 × (V_RT – V_RB)
b) Since R_L, R_OB and R_OT have similar behaviour with respect to process and temperature variation, the ratio
R-----_O^----_B^----+^{-----RR----L-}_L^----+^-----R----_O^----_T^{- will be kept reasonably constant from part to part. Consequently variation of the output codes}
at a given input voltage depends mainly on the difference V_RT − V_RB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
1996 Mar 20
8